uTemps Utile pcb v1.0

£10.40 (exc VAT)

8hp version of Temps utile 6x clock generator by MXMXMX.

PCB redesign by J. Matheson. it works with the same firmware.

Temps Utile original wiki

BOM

Github

… a fairly simple breakout board for teensy 3.1/3.2, focused on clock sequencing

(the name may suggest as much … it was stolen from M. Louis Lapicque (see: idem, 1907: Sur l’excitation par décharge de condensateurs; détermination directe de la durée et de la quantité utiles. Comptes Rendus Soc. Biol. (Paris) 62, 701-704).

hardware basics, in brief:

  • teensy 3.1/3.2 @ 120MHz, w/ 128×64 OLED
  • trigger-to-output latency < 100us.
  • 2 clock inputs (> 100k input impedance; threshold ~ 2.5V)
  • 4 CV inputs (100k input impedance, -/+ 5V, assignable to (almost) any parameter)
  • 6 clock outputs (5 digital, 1 DAC (12 bit): 10V (GPIO), -/+ 6V (DAC))
  • two encoders w/ switches; 2 tactile buttons.
  • 14HP, ~ 25 mm Depth

firmware:

  • 7 modes, selectable per channel:
    • trigger sequencer/sequence editor
    • clock division/multiplication
    • LFSR
    • random w/ threshold
    • euclidian
    • logic (AND, OR, XOR, NAND, NOR, XNOR)
    • burst
    • DAC (channel #4 only): random, binary, “Turing”, logistic, sequencer/arpeggiator

In stock

Additional information

Weight 15 g
Dimensions 110 × 35 × 2 mm
description

Synthesiser parts/components

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